Pentium(R) 4 processor topic64k/M Aliasing Conflicts Performance Impact

Thread Specificity: TS

This event counts the number of 64K-aliasing conflicts.  A 64K-aliasing conflict occurs when a virtual address memory references a cache line that is modulo 64K bytes apart from another cache line that already resides in the first level cache.  Only one cache line with a virtual address modulo 64K bytes can reside in the first level cache at the same time.

For example, accessing a byte at virtual addresses 0x10000 and 0x3000F would cause a 64K aliasing conflict.  This is because the virtual addresses for the two bytes reside on cache lines that are modulo 64K bytes apart.

On the Intel® Pentium® 4 and Intel® Xeon™ processors with CPUID signature of family encoding 15, model encoding of 0, 1 or 2, the 64K aliasing conflict also occurs when addresses have identical value in bits 15:6. If you avoid this kind of aliasing, you can speedup programs by a factor of three if they load frequently from preceding stores with aliased addresses and there is little other instruction-level parallelism available. The gain is smaller when loads alias with other loads, which cause thrashing in the first-level cache.


This is not a precise event. 64K aliasing events are counted more than once per conflict.

See Also Additional Events that Indicate Coding Pitfalls:

Split Loads Retired

MOB Load Replays Retired (Blocked Store-to-Load Forwards Retired)

Streaming SIMD Extensions (SSE) Input Assists

x87 Input Assists

x87 Output Assists