MOVDQU - Move Unaligned Double Quadword

Opcode

Instruction

Description

F3 0F 6F /r

MOVDQU xmm1, xmm2/m128

Move unaligned double quadword from xmm2/m128 to xmm1.

F3 0F 7F /r

MOVDQU xmm2/m128, xmm1

Move unaligned double quadword from xmm1 to xmm2/m128.

Description

Moves a double quadword from the source operand (second operand) to the destination operand (first operand). This instruction can be used to move a double quadword to and from an XMM register and a 128-bit memory location, or between two XMM registers. When the source or destination operand is a memory operand, the operand may be unaligned on a 16-byte boundary without causing a general-protection exception (#GP) to be generated.

To move a double quadword to or from memory locations that are known to be aligned on 16-byte boundaries, use the MOVDQA instruction.

Operation

DEST SRC;
* #GP if SRC or DEST unaligned memory operand *;

Intel® C++ Compiler Intrinsic Equivalent

MOVDQU void _mm_storeu_si128 ( __m128i *p, __m128i a) MOVDQU __m128i _mm_loadu_si128 ( __m128i *p)

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#NM - If TS in CR0 is set.

#UD - If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.

#PF(fault-code) - If a page fault occurs.

Real-Address Mode Exceptions

#GP(0) - If any part of the operand lies outside of the effective address space from 0 to FFFFH.

#NM - If TS in CR0 is set.

#UD - If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#PF(fault-code) - For a page fault.