MOVNTI - Move Doubleword Non-Temporal




0F C3 /r

MOVNTI m32, r32

Move doubleword from r32 to m32, minimizing pollution in the cache hierarchy.


Moves the doubleword integer in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to minimize cache pollution during the write to memory. The source operand is a general-purpose register. The destination operand is a 32-bit memory location.

The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an uncacheable (UC) or write protected (WP) memory region.

Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation such as SFENCE should be used in conjunction with MOVNTI instructions if multiple processors might use different memory types to read/write the memory location.



Intel® C++ Compiler Intrinsic Equivalent

MOVNTDQ void_mm_stream_si32 (int *p, int a)

SIMD Floating-Point Exceptions


Protected Mode Exceptions

#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.

#SS(0) - For an illegal address in the SS segment.

#PF(fault-code) - For a page fault.

#NM - If TS in CR0 is set.

#UD - If EM in CR0 is set. If CPUID feature flag SSE2 is 0.

Real-Address Mode Exceptions

#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment.

Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.

#NM - If TS in CR0 is set.

#UD - If EM in CR0 is set. If CPUID feature flag SSE2 is 0.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode

#PF(fault-code) - For a page fault.