PREFETCHh--Prefetch Data Into Caches




0F 18 /1


Move data specified by address closer to the processor using T0 hint.

0F 18 /2


Move data specified by address closer to the processor using T1 hint.

0F 18 /3


Move data specified by address closer to the processor using T2 hint.

0F 18 /0


Move data specified by address closer to the processor using NTA hint.


Fetches the line of data from memory that contains the byte specified with the source operand to a location in the cache hierarchy specified by a locality hint:

    T0 (temporal data)--prefetch data into all cache levels.

    T1 (temporal data with respect to first level cache)--prefetch data in all cache levels except 0th cache level

    T2 (temporal data with respect to second level cache) --prefetch data in all cache levels, except 0th and 1st cache levels.

    NTA (non-temporal data with respect to all cache levels)--prefetch data into non-temporal cache structure. (This hint can be used to minimize pollution of caches.)

The source operand is a byte memory location. (The locality hints are encoded into the machine level instruction using bits 3 through 5 of the ModR/M byte. Use of any ModR/M value other than the specified ones will lead to unpredictable behavior.)

If the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement occurs. Prefetches from uncacheable or WC memory are ignored.

The PREFETCHh instruction is merely a hint and does not affect program behavior. If executed, this instruction moves data closer to the processor in anticipation of future use.

The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a processor implementation. The amount of data prefetched is also processor implementation-dependent. It will, however, be a minimum of 32 bytes.

It should be noted that processors are free to speculatively fetch and cache data from system memory regions that are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). The PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not tied to instruction execution, PREFETCHh instructions are not ordered with respect to the fencing instructions (MFENCE, SFENCE, LFENCE) or locked memory references. It is also unordered with respect to CLFLUSH instructions, other PREFETCHh instructions, or any other general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, and OUT, and MOV CR.


FETCH (m8);

Intel® C++ Compiler Intrinsic Equivalent

void_mm_prefetch(char *p, int i)

The argument "*p" gives the address of the byte (and corresponding cache line) to be prefetched. The value "i" gives a constant (_MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2, or _MM_HINT_NTA) that specifies the type of prefetch operation to be performed.

Numeric Exceptions


Protected Mode Exceptions


Real Address Mode Exceptions


Virtual 8086 Mode Exceptions