ia Branch Type

The branch is taken unconditionally, if it is not intercepted by the OS. The effect of the branch is to invoke the IA-32 instruction set (by setting PSR.is to 1) and begin processing IA-32 instructions at the virtual linear target address contained in BR b2{31:0}. If the qualifying predicate is not PR 0, an Illegal Operation fault is raised. If instruction set transitions are disabled (PSR.di is 1), then a Disabled Instruction Set Transition fault is raised.

The IA-32 target effective address is calculated relative to the current code segment, i.e. EIP{31:0} = BR b2{31:0} – CSD.base. The IA-32 instruction set can be entered at any privilege level, provided PSR.di is 0. If PSR.dfh is 1, a Disabled FP Register fault is raised on the target IA-32 instruction. No register bank switch nor change in privilege level occurs during the instruction set transition.

Software must ensure the code segment descriptor (CSD) and selector (CS) are loaded before issuing the branch. If the target EIP value exceeds the code segment limit or has a code segment privilege violation, an IA-32_Exception (GPFault) is raised on the target IA-32 instruction. For entry into 16-bit IA-32 code, if BR b2 is not within 64K-bytes of CSD.base a GPFault is raised on the target instruction. EFLAG.rf is unmodified until the successful completion of the first IA-32 instruction. PSR.da, PSR.id, PSR.ia, PSR.dd, and PSR.ed are cleared to zero after br.ia completes execution and before the first IA-32 instruction begins execution. EFLAG.rf is not cleared until the target IA-32 instruction successfully completes.

Software must issue a mf instruction before the branch if memory ordering is required between IA-32 processor consistent and Itanium®-based system unordered memory references. The processor does not ensure Intel® Itanium® instruction set generated writes into the instruction stream are seen by subsequent IA-32 instruction fetches. br.ia does not perform an instruction serialization operation. The processor does ensure that prior writes (even in the same instruction group) to GRs, FRs and ARs are observed by the first IA-32 instruction. Writes to ARs within the same instruction group as br.ia are not allowed, since br.ia may implicitly read all ARs.

IA-32 instruction set execution destroys the contents of the ALAT. Software can not rely on ALAT values being preserved across an instruction set transition. On entry to IA-32 code, existing entries in the ALAT are ignored. If the register stack contains any dirty registers, an Illegal Operation fault is raised on the br.ia instruction. All registers left in the current register stack frame are destroyed during IA-32 instruction set execution. The current register stack frame is forced to zero. To flush the register file of dirty registers, the flushrs instruction must be issued in an instruction group proceeding the br.ia instruction. To enhance the performance of the instruction set transition, software can start the Itanium-based system register stack flush in parallel with starting the IA-32 instruction set by 1) ensuring flushrs is exactly one instruction group before the br.ia, and 2) br.ia is in the first B-slot. br.ia should always be executed in the first B-slot with a hint of “static-taken” (default), otherwise processor performance will be degraded.

If a br.ia causes any traps on an Itanium-based system (e.g., Single Step trap, Taken Branch trap, or Unimplemented Instruction Address trap), IIP will contain the original 64-bit target IP. (The value will not have been zero extended from 32 bits.)