Intel XScale(R) technology topicData-processing Operands Overview

The Data-processing Operands addressing mode is divided into 11 submodes. They are used to calculate a shifter operand in a data-processing instruction. The general syntax for this addressing mode is provided in the following section.

General Syntax

opcode [condition] [S] dest, op1, addr_mode

where:

 opcode

Specifies the instruction's operation.

 condition

Is one of 16 conditions. See Condition Code Status.

 S

Update condition code flag (bit 20)

 dest

Specifies the destination register.

 op1

Specifies the register containing the first operand.

 

 addr_mode can be one of the following 11 submodes:

Submode

Description

 # imm

Provides a constant operand to a data-processing instruction. See Data Processing Operands: Immediate (AM 1).

 op2

Provides a register value. See Data-Processing Operands: Register (AM 1).

 op2 , ASR # sh_imm

Provides the value of a register, arithmetically shifted right by sh_imm . See Data-Processing Operands: Arithmetic Shift Right by Immediate (AM 1).

 op2 , ASR op3

Provides the value of a register, arithmetically shifted right by the value in register op3 . See Data-Processing Operands: Arithmetic Shift Right by Register (AM 1).

 op2 , LSL # sh_imm

Provides the value of a register, logically shifted left by sh_imm . See Data-Processing Operands: Logical Shift Left by Immediate (AM 1).

 op2 , LSL op3

Provides the value of a register, logically shifted left by the value in register op3 . See Data-Processing Operands: Logical Shift Left by Register (AM 1).

 op2 , LSR # sh_imm

Provides the value of a register, logically shifted right by sh_imm . See Data-Processing Operands: Logical Shift Right by Immediate (AM 1).

 op2 , LSR op3

Provides the value of a register, logically shifted right by the value in register op3 . See Data-Processing Operands: Logical Shift Right by Register (AM 1).

 op2 , ROR # sh_imm

Provides the value of a register, rotated by sh_imm . See Data-Processing Operands: Rotate Right by Immediate (AM 1).

 op2 , ROR op3

Provides the value of a register, rotated by the value in register op3 . See Data-Processing Operands: Rotate Right by Register (AM 1).

 op2 , RRX

Provides the value of a register, rotated by one bit. See Data-Processing Operands: Rotate Right with Extend (AM 1).

 

General Encoding

The following tables show the encodings for Addressing Mode 1:

  

Encoding - Addressing Mode 1, 32-bit Immediate

31

 

 

28

27

26

25

24

 

 

21

20

19

 

 

16

 condition

 0

 0

 1

 opcode

 S

 op1

15

 

 

12

11

 

 

8

7

 

 

 

 

 

 

0

 dest

 rt_imm

 imm_8

  

Encoding - Addressing Mode 1, Immediate Shift

31

 

 

28

27

26

25

24

 

 

21

20

19

 

 

16

 condition

 0

 0

 0

 opcode

 S

 op1

15

 

 

12

11

 

 

 

7

6

5

4

3

 

 

0

 dest

 sh_imm

 shift

 0

 op2

 

Encoding - Addressing Mode 1, Register Shift

31

 

 

28

27

26

25

24

 

 

21

20

19

 

 

16

 condition

 0

 0

 0

 opcode

 S

 op1

15

 

 

12

11

 

 

8

7

6

5

4

3

 

 

0

 dest

 op3

 0

 shift

 1

 op2

 

where:

Bit [11:0]

Contain the shifter operand. For more information refer to the Shifter Operand.

Bit [25]

Is the I bit. It is used to distinguish between an immediate shifter operand and a register-based shifter operand.

Note

If all bits shown below have the following values, the instruction is not a data-processing instruction, but lies in the arithmetic or Load/Store instruction extension space:

     bit [25]

     == 

     0 

     bit [4]

     == 

     1 

     bit [7]

     == 

     1 

The Shifter Operand

The shifter operand is created by the shifter. The shifter produces a carry-out, which is written to the carry flag by some instructions. The first source operand register op1 uses the form register shift left by immediate, with the immediate set to zero.

The shifter operand can take one of three following basic formats:

  • Immediate operand value
  • Register operand value
  • Shifted register operand value

These formats are described in the following sections.

Immediate Operand Value

An immediate operand value is created by rotating an 8-bit constant by an even number of bits. Hence, each instruction includes an 8-bit constant and a 4-bit rotate to be applied to that constant.

Some valid constants are:

0xFF, 0x14, 0xFF0, 0xFF00, 0xFF000, 0xFF000000, 0xF000000F

Some invalid constants are:

0x101, 0x102, 0xFF1, 0xFF003, 0xFFFFFFF, 0xF000001F

Immediate Operand

ADD R2, R2, #FF

This adds 255 to the value of register R2 .

Register Operand Value

A register operand value is the value of a register. It is used directly as the operand to the data-processing instruction.

Register Operand

ADD R2, R1, R0

This adds the value of R0 to R1 . The result is stored in R2 .

Shifted Register Operand Value

A shifted register operand value is the value of a register, that has been shifted or rotated before it is used as operand to the data-processing instruction. There are five types of shift:

 ASR

Arithmetic shift right

 LSL

Logical shift left

 LSR

Logical shift right

 ROR

Rotate right

 RRX

Rotate right with extend

 

The number of bits to shift can be specified either as an immediate or a register value.

Shifted Register Operand

MOV R4, R2, LSL #3

This shifts R2 by three and writes the value to R4 .

 

Further Information

See Assembler Instructions