This event initiates time-based sampling by setting the counters to count the processor's clock ticks.
Also referred to as a clock or a CPU cycle, a clocktick is the smallest unit of time recognized by the processor. The term is also used to indicate the time required by the processor to execute an instruction.
There are two ways to count processor clocks.
The time stamp counter increments whenever the chip is not in deep-sleep mode. It can be read with the RDTSC instruction. The difference in values between two reads (modulo 2**64) gives the number of processor clocks between those reads.
The performance monitoring counters can also be configured to count clocks whenever the chip is not in deep sleep mode.
To count clocks with a performance monitoring counter, do the following:
Select any one of the 18 counters.
Select any of the possible ESCRs whose events the selected counter can count, and set its event select to anything other than no_event. This may not seem necessary, but the counter may be disabled in some cases if this is not done.
Turn threshold comparison on in the CCCR by setting the compare bit to 1.
Set the threshold to 15 and the complement to 1 in the CCCR. Since no event can ever exceed this threshold, the threshold condition is met every cycle, and hence the counter counts every cycle.
Enable counting in the CCCR for that counter by setting the enable bit.
The second alternative for counting clocks is useful where counter overflow is used to generate an interrupt and for those cases where it is easier for a tool to read a performance counter instead of the time stamp counter.