LDMXCSR--Load Streaming SIMD Extension Control/Status

Description

The MXCSR control/status register is used to enable masked/unmasked exception handling, to set rounding modes, to set flush-to-zero mode, and to view exception status flags. The following figure shows the format and encoding of the fields in MXCSR:

The default MXCSR value at reset is 0x1f80.

Bits 5-0 indicate whether a Streaming SIMD Extension numerical exception has been detected. They are "sticky" flags, and can be cleared by using the LDMXCSR instruction to write zeros to these fields. If an LDMXCSR instruction clears a mask bit and sets the corresponding exception flag bit, an exception will not be immediately generated. The exception will occur only upon the next Streaming SIMD Extension to cause this type of exception. Streaming SIMD Extension uses only one exception flag for each exception. There is no provision for individual exception reporting within a packed data type. In situations where multiple identical exceptions occur within the same instruction, the associated exception flag is updated and indicates that at least one of these conditions happened. These flags are cleared upon reset.

Bits 12-7 configure numerical exception masking. An exception type is masked if the corresponding bit is set, and unmasked if the bit is clear. These enables are set upon reset, meaning that all numerical exceptions are masked.

Bits 14-13 encode the rounding control, which provides for the common round to nearest mode, as well as directed rounding and true chop. Rounding control affects the arithmetic instructions and certain conversion instructions. The encoding for RC is as follows:

The rounding control is set to round to nearest upon reset.

Bit 15 (FZ) is used to turn on the Flush-To-Zero mode (bit is set). Turning on the Flush-To-Zero mode has the following effects during underflow situations:

• zero results are returned with the sign of the true result

• precision and underflow exception flags are set

The IEEE mandated masked response to underflow is to deliver the denormalized result (i.e., gradual underflow); consequently, the flush-to-zero mode is not compatible with IEEE Std. 754. It is provided primarily for performance reasons. At the cost of a slight precision loss, faster execution can be achieved for applications where underflows are common. Unmasking the underflow exception takes precedence over Flush-To-Zero mode. This arrangement means that an exception handler will be invoked for a Streaming SIMD Extension that generates an underflow condition while this exception is unmasked, regardless of whether flush-to-zero is enabled.

The other bits of MXCSR (bits 31-16 and bit 6) are defined as reserved and cleared; attempting to write a non-zero value to these bits, using either the FXRSTOR or LDMXCSR instructions, will result in a general protection exception.

The linear address corresponds to the address of the least-significant byte of the referenced memory data.

Operation

MXCSR m32;

C++ Compiler Intrinsic Equivalent

_mm_setcsr(unsigned int i)

Sets the control register to the value specified.

Exceptions

General protection fault if reserved bits are loaded with non-zero values.

Numeric Exceptions

None.

Protected Mode Exceptions

#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments.

#SS(0) - For an illegal address in the SS segment.

#PF(fault-code) - For a page fault.

#UD - If CR0.EM 1.

#NM - If TS bit in CR0 is set.

#AC - for unaligned memory reference. To enable #AC exceptions, three conditions must be true(CR0.AM is set; EFLAGS.AC is set; current CPL is 3). #UD If CR4.OSFXSR(bit 9) 0. #UD If CPUID.XMM(EDX bit 25) 0.

Real Address Mode Exceptions

Interrupt 13 - If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.

#UD - If CR0.EM 1.

#NM - If TS bit in CR0 is set.

#UD - If CR4.OSFXSR(bit 9) 0. #UD If CPUID.XMM(EDX bit 25) 0.

Virtual 8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#PF(fault-code) - For a page fault.

#AC - For unaligned memory reference.

Comments

The usage of Repeat Prefix (F3H) with LDMXCSR is reserved. Different processor implementations may handle this prefix differently. Usage of this prefix with LDMXCSR risks incompatibility with future processors.