Opcode |
Instruction |
Description |
F3 0F 5A /r |
CVTSS2SD xmm1, xmm2/m32 |
Convert one single-precision floating-point value in xmm2/m32 to one double-precision floating-point value in xmm1. |
Converts a single-precision floating-point value in the source operand (second operand) to a double-precision floating-point value in the destination operand (first operand). The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register. The result is stored in the low quadword of the destination operand, and the high quadword is left unchanged.
DEST[63-0] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31-0]);
* DEST[127-64] remains unchanged *;
CVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 b)
Invalid, Denormal.
#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0) - For an illegal address in the SS segment.
#PF(fault-code) - For a page fault.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.
#AC - For unaligned memory reference if the current privilege level is 3.
Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.
Same exceptions as in Real Address Mode.
#PF(fault-code) - For a page fault.
#AC - For unaligned memory reference if the current privilege level is 3.