Flush Cache InstructionFlush Cache Instructionfc
Instruction Type M
Format
(qp) fc r3
Description
The cache line associated with the address specified by the value of GR r3 is invalidated from all levels of the processor cache hierarchy. The invalidation is broadcast throughout the coherence domain. If, at any level of the cache hierarchy, the line is inconsistent with memory it is written to memory before invalidation.
The line size affected is at least 32-bytes (aligned on a 32-byte boundary). An implementation may flush a larger region.
When executed at privilege level 0, fc performs no access rights or protection key checks. At other privilege levels, fc performs access rights checks as if it were a 1-byte read, but no protection key checks (regardless of PSR.pk).
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. This instruction can be used to remove a range of addresses from the cache by first changing the memory attribute to non-cacheable and then flushing the range.
This instruction follows data dependency rules; it is ordered with respect to preceding and following memory references to the same line. fc has data dependencies in the sense that any prior stores by this processor will be included in the data written back to memory. fc is an unordered operation, and is not affected by a memory fence (mf) instruction. It is ordered with respect to the sync.i instruction.