Immediate Post-indexed (AM 2)

Syntax

[basereg], #+/-value

where:

basereg	Specifies a register containing the base address.
value	Specifies the 12-bit immediate offset used with the value of basereg to form the address.

Description

The addressing mode "immediate post-indexed" performs the following operation (pseudo-code description):

addr = basereg
if ConditionPassed (condition) then
if U == 1 then
   basereg = basereg + value
else/* U == 0 */
   basereg = basereg - value

This addressing mode uses the value of the base register basereg as the address for the memory access.

The value of the immediate offset is added to or subtracted from the value of the base register basereg if the condition specified in the instruction matches the condition code status. Then it is written back to basereg .

This addressing mode is useful for pointer access to arrays with automatic update of the pointer value.

Encoding

31			28	27	26	25	24	23	22	21	20	19			16
condition				0	1	0	0	U	B	0	L	basereg

15			12	11											0
dest				value

The B bit indicates an unsigned byte ( B==1 ) or a word access ( B==0 ).

The L bit indicates a Load ( L==1 ) or a Store ( L==0 ) instruction.

Note

The instructions LDRBT , LDRT , STRBT , and STRT support only post-indexed addressing modes. For these instructions, the above bit pattern is modified:
bit[21] (the W bit) is 1, not 0 as shown above.

The syntax [basereg] is treated as an abbreviation for [basereg], #0 for instructions which only support post-indexed addressing modes ( LDRBT , LDRT , STRBT , or STRT ). For all other instructions, the syntax [basereg] is not treated as an abbreviation for [basereg], #0 .

Caution

If R15 is specified as register basereg , the results are unpredictable.

Example

LDR    R9, [R7], #5

Further Information

See Addressing Mode 2: Load and Store Word or Unsigned Byte
See Assembler Instructions