Overview - Load and Store Word or Unsigned Byte

The Load and Store Word or Unsigned Byte addressing mode is divided into 9 submodes. They are used to calculate the address for a load and store unsigned byte instruction. The general syntax for this addressing mode is provided in the following section.

General Syntax

LDR|STR [condition] [B] [T] dest, addr_mode

where:

LDR	Specifies Load Register instruction.
STR	Specifies Store Register instruction.
condition	Is one of 16 conditions. See Condition Code Status.
B	Extends the instruction to the Load Register Byte (LDRB) instruction or to the Store Register Byte ( STRB ) instruction. For further information see LDRB Instruction or STRB Instruction.
T	Extends the instruction to the Load Register with Translation (LDRT) instruction or to the Store Register with Translation ( STRT ) instruction. For further information see LDRT Instruction or STRT Instruction.
dest	Specifies the destination register.

addr_mode can be one of the following 9 submodes:

Submode	Description
[ basereg , #+/- value ]	Offset option: Adds or subtracts the value of a 12-bit immediate offset to or from the base register. See Load/Store Word or Unsigned Byte: Immediate Offset (AM 2).
[ basereg , +/- indexreg ]	Offset option: Adds or subtracts the value of an index register to or from the base register. See Load/Store Word or Unsigned Byte: Register Offset (AM 2).
[ basereg , +/- indexreg , shift # sh_imm ]	Offset option: Adds or subtracts the shifted or rotated value of an index register to or from the base register. shift specifies one of five shift types. See Load/Store Word or Unsigned Byte: Scaled Register Offset (AM 2).
[ basereg #+/- value ]!	Pre-indexed option: Adds or subtracts the value of a 12-bit immediate offset to or from the base register. The value is written back to the base register if a condition is passed. See Load/Store Word or Unsigned Byte: Immediate Pre-indexed (AM 2).
[ basereg , +/- indexreg ]!	Pre-indexed option: Adds or subtracts the value of an index register to or from the base register. The value is written back to the base register if a condition is passed. See Load/Store Word or Unsigned Byte: Register Pre-indexed (AM 2).
[ basereg , +/- indexreg , shift # sh_imm ]!	Pre-indexed option: Adds or subtracts the shifted or rotated value of an index register to or from the base register. The value is written back to the base register if a condition is passed. shift specifies one of five shift types. See Load/Store Word or Unsigned Byte: Scaled Register Pre-indexed (AM 2).
[ basereg ], #+/- value	Post-indexed option: Adds or subtracts the value of a 12-bit immediate offset to or from the base register if a condition is passed. Then the value is written back to the base register. See Load/Store Word or Unsigned Byte: Immediate Post-indexed (AM 2).
[ basereg ], +/- indexreg	Post-indexed option: Adds or subtracts the value of an index register to or from the base register if a condition is passed. Then the value is written back to the base register. See Load/Store Word or Unsigned Byte: Register Post-indexed (AM 2).
[ basereg ], +/- indexreg , shift # sh_imm	Post-indexed option: Adds or subtracts the shifted or rotated value of an index register to or from the base register if a condition is passed. Then the value is written back to the base register. shift specifies one of five shift types. See Load/Store Word or Unsigned Byte: Scaled Register Post-indexed (AM 2).

All nine of the submodes above are available for the instructions LDR , LDRB , STR , and STRB . For the instructions LDRBT , LDRT , STRBT , and STRBT , only the post-indexed options are available. For the instruction PLD , only the offset options are available.

General Encoding

The following tables show the encodings for Addressing Mode 2:

Encoding - Addressing Mode 2, Immediate Offset/Index

31			28	27	26	25	24	23	22	21	20	19			16
condition				0	1	0	P	U	B	W	L	basereg

15			12	11											0
dest				value

Encoding - Addressing Mode 2, Register Offset/Index

31			28	27	26	25	24	23	22	21	20	19			16
condition				0	1	1	P	U	B	W	L	basereg

15			12	11	10	9	8	7	6	5	4	3			0
dest				0	0	0	0	0	0	0	0	indexreg

Encoding - Addressing Mode 2, Scaled Register Offset/Index

31			28	27	26	25	24	23	22	21	20	19			16
condition				0	1	1	P	U	B	W	L	basereg

15			12	11				7	6	5	4	3			0
dest				sh_imm					shift		0	indexreg

where:

P	P == 0 indicates post-indexed addressing. The base register value is used for the memory address. Then the offset is applied to the base register value and written back to the base register. P == 1 indicates offset addressing or pre-indexed addressing. (This is determined by the W bit.) The memory address is generated by applying the offset to the base register value.
U	Indicates whether the offset is added to the base or subtracted from the base: If U== 1 the offset is added to the base. If U == 0 the offset is subtracted from the base.
B	Indicates an unsigned byte or a word access: B == 1 indicates an unsigned byte. B == 0 indicates a word access.
L	Indicates a Load or a Store: L == 1 indicates a Load. L == 0 indicates a Store.

The meaning of W depends on the setting of P :

	P==0	P==1
W==0	The instruction is LDR , LDRB , STR , or STRB . A normal memory access is performed.	The base register is not updated (offset addressing).
W==1	The instruction is LDRBT , LDRT , STRBT , or STRT . An unprivileged memory access is performed.	The calculated memory address is written back to the base register (pre-indexed addressing).

Further Information

See Assembler Instructions