FXRSTOR--Restore x87 FPU, MMX(TM) Technology, Streaming SIMD Extensions, and Streaming SIMD Extensions 2 State

Description

Reloads the x87 FPU, MMX technology, Streaming SIMD Extensions, and Streaming SIMD Extensions 2 data, control, and status registers from the source operand. The source operand is a 512-byte memory location. This data should have been written to memory previously using the FXSAVE instruction. Layout of FXSAVE and FXRSTOR Memory Region shows the layout of the state information in memory. Three fields in the floating-point save area contain reserved bits that are not indicated in the table:

FOP The lower 11-bits contain the opcode, upper 5-bits are reserved. IP and DP 32-bit mode: 32-bit IP-offset. 16-bit mode: lower 16 bits are IP-offset and upper 16 bits are reserved.

If the MXCSR state contains an unmasked exception with a corresponding status flag also set, loading it will not result in a floating-point error condition being asserted. Only the next occurrence of this unmasked exception will result in the error condition being asserted.

Some bits of MXCSR (bits 31-16 and bit 6) are defined as reserved and cleared; attempting to write a non-zero value to these bits will result in a general protection exception.

The FXRSTOR instruction does not flush pending x87 FPU exceptions, unlike the FRSTOR instruction does. To check and raise exceptions when loading a new operating environment, use an FWAIT instruction after the FXRSTOR instruction.

The Streaming SIMD Extensions fields in the save image (XMM0-XMM7 and MXCSR) may not be loaded into the processor if the CR4.OSFXSR bit is not set. This CR4 bit must be set in order to enable execution of Streaming SIMD Extensions.

State saved with FXSAVE and restored with FRSTOR, and state saved with FSAVE and restored with FXRSTOR, will result in incorrect restoration of state in the processor. The address size prefix will have the usual effect on address calculation, but will have no effect on the format of the FXRSTOR image.

Operation

Load x87 FPU, MMX technology, SSE, and SSE2 state SRC;

Layout of FXSAVE and FXRSTOR Memory Region

x87 FPU and SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments, or if an attempt is made to load non-zero values to reserved bits in the MXCSR field. If memory operand is not aligned on a 16-byte boundary, regardless of segment.

#SS(0) - For an illegal address in the SS segment.

#PF (fault-code) - For a page fault.

#NM - If CR0.EM 1.

#NM - If TS bit in CR0 is set.

#UD - If instruction is preceded by a LOCK override prefix

#AC - For unaligned memory reference if the current privilege level is 3. If #AC is enabled (and CPL is 3), signaling of #AC is not guaranteed and may vary with implementation. In all implementations where #AC is not signaled, a general protection fault will instead be signaled. In addition, the width of the alignment check when #AC is enabled may also vary with implementation; for instance, for a given implementation, #AC might be signaled for a 2-byte misalignment, whereas #GP might be signaled for all other misalignments (4-, 8-, or 16-byte).

Real Address Mode Exceptions

#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment.

Interrupt 13 - If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.

#NM - If CR0.EM 1.

#NM - If TS bit in CR0 is set.

#UD - If instruction is preceded by a LOCK override prefix

Virtual 8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#AC - For unaligned memory reference if the current privilege level is 3.

#PF (fault-code) - For a page fault.