Load Instructionld
Instruction Type M
Format
(qp) ldsz.ldtype.ldhint r1 = [r3] no_base_update_form
(qp) ldsz.ldtype.ldhint r1 = [r3], r2 reg_base_update_form
(qp) ldsz.ldtype.ldhint r1 = [r3], imm9 imm_base_update_form
(qp) ld8.fill.ldhint r1 = [r3] fill_form, no_base_update_form
(qp) ld8.fill.ldhint r1 = [r3], r2 fill_form, reg_base_update_form
(qp) ld8.fill.ldhint r1 = [r3], imm9 fill_form, imm_base_update_form
Description
A value consisting of sz bytes is read from memory starting at the address specified by the value in GR r3. The value is then zero extended and placed in GR r1. The NaT bit corresponding to GR r1 is cleared, except as described below for speculative loads. The ldtype completer specifies special load operations.
For the fill_form, an 8-byte value is loaded, and a bit in the UNAT application register is copied into the target register NaT bit. This instruction is used for reloading a spilled register/NaT pair.
In the base update forms, the value in GR r3 is added to either a signed immediate value (imm9) or a value from GR r2, and the result is placed back in GR r3. This base register update is done after the load, and does not affect the load address. In the reg_base_update_form, if the NaT bit corresponding to GR r2 is set, then the NaT bit corresponding to GR r3 is set and no fault is raised.
For the non-speculative load types, if NaT bit associated with GR r3 is 1, a Register NaT Consumption fault is taken. For speculative and speculative advanced loads, no fault is raised, and the exception is deferred. For the base-update calculation, if the NaT bit associated with GR r2 is 1, the NaT bit associated with GR r3 is set to 1 and no fault is raised.
The value of the ldhint completer specifies the locality of the memory access. A prefetch hint is implied in the base update forms. The address specified by the value in GR r3 after the base update acts as a hint to prefetch the indicated cache line. This prefetch uses the locality hints specified by ldhint. Prefetch and locality hints do not affect program functionality and may be ignored by the implementation.
In the no_base_update form, the value in GR r3 is not modified and no prefetch hint is implied.
For the base update forms, specifying the same register address in r1 and r3 will cause an Illegal Operation fault.