Floating-point Load Instruction

ldf

Operation Font Conventions

Instruction Type M

Format

(qp) ldffsz.fldtype.ldhint f1 = [r3] no_base_update_form

(qp) ldffsz.fldtype.ldhint f1 = [r3], r2 reg_base_update_form

(qp) ldffsz.fldtype.ldhint f1 = [r3], imm9 imm_base_update_form

(qp) ldf8.fldtype.ldhint f1 = [r3] integer_form, no_base_update_form

(qp) ldf8.fldtype.ldhint f1 = [r3], r2 integer_form, reg_base_update_form

(qp) ldf8.fldtype.ldhint f1 = [r3], imm9 integer_form, imm_base_update_form

(qp) ldf.fill.ldhint f1 = [r3] fill_form, no_base_update_form

(qp) ldf.fill.ldhint f1 = [r3], r2 fill_form, reg_base_update_form

(qp) ldf.fill.ldhint f1 = [r3], imm9 fill_form, imm_base_update_form

Description

A value consisting of fsz bytes is read from memory starting at the address specified by the value in GR r3. The value is then converted into the floating-point register format and placed in FR f1. The fldtype completer specifies special load operations.

For the integer_form, an 8-byte value is loaded and placed in the significand field of FR f1 without conversion. The exponent field of FR f1 is set to the biased exponent for 2.063 (0x1003E) and the sign field of FR f1 is set to positive(0).

For the fill_form, a 16-byte value is loaded, and the appropriate fields are placed in FR f1 without conversion. This instruction is used for reloading a spilled register.

In the base update forms, the value in GR r3 is added to either a signed immediate value (imm9) or a value from GR r2, and the result is placed back in GR r3. This base register update is done after the load, and does not affect the load address. In the reg_base_update_form, if the NaT bit corresponding to GR r2 is set, then the NaT bit corresponding to GR r3 is set and no fault is raised.

For the non-speculative load types, if NaT bit associated with GR r3 is 1, a Register NaT Consumption fault is taken. For speculative and speculative advanced loads, no fault is raised, and the exception is deferred. For the base-update calculation, if the NaT bit associated with GR r2 is 1, the NaT bit associated with GR r3 is set to 1 and no fault is raised.

The value of the ldhint modifier specifies the locality of the memory access. A prefetch hint is implied in the base update forms. The address specified by the value in GR r3 after the base update acts as a hint to prefetch the indicated cache line. This prefetch uses the locality hints specified by ldhint. Prefetch and locality hints do not affect program functionality and may be ignored by the implementation.

In the no_base_update form, the value in GR r3 is not modified and no prefetch hint is implied.

The PSR.mfl and PSR.mfh bits are updated to reflect the modification of FR f1.

Hardware support for ldfe (10-byte) instructions that reference a page that is neither a cacheable page with write-back policy nor a NaTPage is optional. On processor models that do not support such ldfe accesses, an Unsupported Data Reference fault is raised when an unsupported reference is attempted. The fault is delivered only on the normal, advanced, and check load flavors. Control-speculative flavors of ldfe always defer the Unsupported Data Reference fault.

Floating-point Load Instruction

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